The dynamic range of an analog-to-digital converter (ADC) is the ratio of the maximum signal applied at the input to the smallest detectable value. The resolution of an ADC refers to its smallest resolvable input step or smallest detectable value, which is determined by the quantization noise. A high resolution over a large dynamic range is expensive, since it requires an ADC with a large effective number of bits (ENOB). For example, when performing analog-to-digital conversion on an input voltage signal, a 9-bit ADC may be sufficient to resolve a voltage of 15.0 μV within a 10-millivolt range. However, to obtain the same resolution within a 1-volt range would require a 16-bit ADC. Each additional bit of an ADC adds to the overall cost and power consumption, and lowers the conversion speed.
Some kinds of ADC use a delta-sigma (As) or sigma delta (EA) modulator (SDM) to sample the analog input and to convert the samples into a digital bitstream output, which can then be processed, for example by a decimation filter, to obtain a digital output value. A sigma-delta ADC incorporates a feedback loop with a digital-to-analog converter (DAC) that performs digital-to-analog conversion on the output bitstream and subtracts the analog feedback signal from the analog input signal. The SDM effectively operates to minimize the difference between input and output. In its forward path, an SDM uses an active loop filter that provides the required input sensitivity and signal-to-noise ratio, and which shapes the quantization noise of a simple comparator (often just a 1-bit comparator) out of the required signal band. SDMs are very well suited for instrumentation and low frequency sensing or DC (direct current) sensing on account of their favorably high resolution and accuracy and relatively low cost. Applications that use SDMs can be analog and mixed-signal front-ends of the type required in medical sensing and imaging, e.g. in amperometry and lab-on-a-chip implementations, for which the analog signals of interest are predominantly DC or very slowly varying. A lab-on-a-chip (LOC) or a micro total analysis system (μTAS) is a device that comprises an integrated circuit in which one or more laboratory functions are realized. Generally, a sensor provides an analog signal input to the device, which must first perform analog-to-digital conversion in order to be able to process the information. Accurate conversion is necessary in order to perform accurate analysis.
An SDM encodes the input signal amplitude into the output bitstream after observing the input over a finite number of clock samples. The number of samples, often referred as the observation interval, determines the time duration of each analog-to-digital conversion step, and translates to the required time and power consumption of each conversion instance. A relevant design aspect is the oversampling ratio (OSR), i.e. the ratio of the input signal frequency to the sampling frequency. A high OSR is associated with a higher and therefore more favorable signal-to-quantization-noise ratio. However, for an SDM ADC with a fixed filter order, clock speed and quantizer resolution, the quantization noise directly determines the smallest input signal that can be resolved, i.e. a large input signal range is associated with a relatively high level of quantization noise in the feedback loop. Therefore, to maintain a certain resolution, increasing the input signal range requires increasing the resolution of the ADC. If the resolution of the ADC is fixed, for example by its specific effective number of bits (ENOB), a larger input signal range will result in lower conversion accuracy.
The accuracy of encoding in the known types of SDM ADCs—for which the accuracy is largely determined by quantization noise—can be improved by extending the observation interval, i.e. to increase the number of clock cycles. Alternatively, a higher order analog filter can be implemented in the SDM, allowing the observation interval to be shortened. Raising the filter order reduces the number of samples that need to be taken in order to achieve the desired accuracy, but higher order filters have lower maximum stable amplitude and also consume more power on account of the increased number of operational amplifiers. Other attempts at improvement are known, for example using a two-step approach with a first rough conversion step using a successive-approximation stage, and a second fine conversion step using an incremental SDM stage. However, such an ADC is expensive to build and also has unfavorably high energy consumption.
Therefore, it is an object of the invention to provide an improved incremental sigma-delta modulator that overcomes the problems outlined above.